PLL520-05/-06/-07/-08/-09
PIN CONFIGURATION
(Top View)
VDDXINXOUTSEL3^SEL2^OEVCONGND12345678161514131211109SEL0^SEL1^GNDCLKCVDDCLKTGNDGNDLow Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
FEATURES
• 100MHz to 200MHz Fundamental Mode Crystal. • Output range: 100 – 200MHz (no multiplication),
200 – 400MHz (2x multiplier), 400 – 800MHz (4x multiplier), or 800MHz – 1GHz (PLL520-09 TSSOP only, 8x multiplier).
• High yield design supports up to 2pF stray
capacitance at 200MHz.
• CMOS (Standard drive PLL520-07 or Selectable
Drive PLL520-06), PECL (Enable low PLL520-08 or Enable high PLL520-05) or LVDS output (PLL520-09).
• Integrated variable capacitors. • Supports 3.3V-Power Supply.
• Available in 16-Pin (TSSOP or 3x3mm QFN)
Note: PLL520-06 only available in 3x3mm. Note: PLL520-07 only available in TSSOP.
PLL 520-0xSEL0^10GND/DRIVSEL*GNDGNDBLOCK DIAGRAM SELOEVCONOscillatorAmplifierw/XINintegratedvaricapsXOUTPLL(PhaseLockedLoop)^: Internal pull-up
*: PLL520-06 pin 12 is output drive select (DRIVSEL) (0 for High Drive CMOS, 1 for Standard Drive CMOS)
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL520-08 PLL520-05 PLL520-06 PLL520-07 PLL520-09
OE
State
QQ0 (Default) Output enabled
1 Tri-state 0 Tri-state 1 (Default)
Output enabled
PLL by-passOE input: Logical states defined by PECL levels for PLL520-08 Logical states defined by CMOS levels for PLL520-05/-06/-
07/-09
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1
VCONGNDThe PLL520-05/-06/-07/-08/-09 is a family of VCXO
ICs specifically designed to pull high frequency fundamental crystals. Their design was optimized to tolerate higher limits of interelectrode capacitance and bonding capacitance to improve yield. They achieve very low current into the crystal resulting in better overall stability. Their internal varicaps allow an on chip frequency pulling, controlled by the VCON input.
XINXOUTSEL2^OE
12131415161VDDDESCRIPTION
11SEL1^98765GNDCLKCVDDCLKT
P520-0x234元器件交易网www.cecb2b.com
PLL520-05/-06/-07/-08/-09
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
PIN DESCRIPTIONS
Name
TSSOP* Pin number
3x3mm QFN* Pin number
Type Description XIN 2 13 I Crystal in connector. XOUT 3 14 I Crystal out connector. OE 6 16 I Output enable pin. VCON 7 1 I Frequency control input (0.3V to 3.0V) GND 8,9, 10, 14 2,3,4,8,12 P Ground (except pin 12 on PLL520-06: DRIVSEL see below).
PLL520-06 only: Drive Select Input. This pin has an internal pull-up that will default DRIVSEL to ‘1’ when not connect to GND. CMOS output of PLL520-06 will be high drive CMOS DRIVSEL** - 12 I when DRIVSEL is set to ‘0’, and will be standard CMOS otherwise.
True output PECL (PLL520-08) or LVDS (PLL520-09)
CLKT 11 5 O (N/C for PLL520-07)
Complementary output PECL (PLL520-08) or LVDS
CLKC 13 7 O (PLL520-09)
(CMOS out for PLL520-07).
SEL0 16 10 I SEL1 15 9 I Multiplier selector pins. These pins have an internal pull-up
that will default SEL to ‘1’ when not connected to GND. SEL2 5 15 I SEL3 4 Not available I VDD 1, 12 6,11 P +3.3V power supply.
* Note: PLL520-06 only available in 3x3mm QFN, PLL520-07 only available in TSSOP.
** Note: DRIVSEL on pin 12 on PLL520-06 only.
FREQUENCY SELECTION TABLE
SEL3* SEL2 SEL1 SEL0 Selected Multiplier 0* 1* 1*
0 0 1
1 1 1
1 1 0
Fin x 8 (PLL520-09 in TSSOP only)
Fin x 4 Fin x 2
No multiplication 1* 1 1 1 Note *: SEL3 is not available (always “1”) in 3x3mm package
All pins have internal pull-ups (default value is 1). Connect to GND to set to 0.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2
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PLL520-05/-06/-07/-08/-09
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage
Input Voltage, dc Output Voltage, dc Storage Temperature
Ambient Operating Temperature* Junction Temperature
Lead Temperature (soldering, 10s) ESD Protection, Human Body Model
VDD 4.6 V VI -0.5 VDD+0.5 V VO -0.5 VDD+0.5 V TS -65 150 °C TA -40 85 °C TJ 125 °C 260 °C 2 kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS SYMBOL CONDITIONS
Crystal Resonator Frequency Crystal Loading Rating Interelectrode Capacitance Crystal Pullability Recommended ESR
MIN. MAX. UNITS FXIN Parallel Fundamental Mode 100 200 MHz
CL (xtal) Die at VCON = 1.65V 4 pF C0 3.5 pF C0/C1 (xtal) AT cut 250 - RE AT cut 30 Ω
3. Voltage Controlled Crystal Oscillator
PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS VCXO Stabilization Time *
TVCXOSTB
From power valid 10 ms
FXIN = 100 – 200MHz; XTAL C0/C1 < 250 200* ppm VCXO Tuning Range
0V ≤ VCON ≤ 3.3V
CLK output pullability ppm VCON=1.65V, ±1.65V ±100* On-chip Varicaps control range VCON = 0 to 3.3V 4 – 18* pF
Linearity 10* % VCXO Tuning Characteristic 65 ppm/V VCON input impedance 60 kΩ VCON modulation BW 25 kHz 0V ≤ VCON ≤ 3.3V, -3dB
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 3
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PLL520-05/-06/-07/-08/-09 =CONDITIONS
=
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
4. General Electrical Specifications
PARAMETERS SYMBOL Supply Current (Loaded
Outputs)
Operating Voltage Output Clock Duty Cycle Short Circuit Current
IDD VDD
MIN. TYP. MAX. UNITS PECL/LVDS/CMOS 100/80/40 mA
2.97 3.63 V @ 50% VDD (CMOS) 45 50 55
% @ 1.25V (LVDS) 45 50 55
@ VDD – 1.3V (PECL) 45 50 55 mA ±50
5. Jitter Specifications
Period jitter RMS Period jitter peak-to-peak Accumulated jitter RMS Accumulated jitter peak-to-peak Random Jitter
Integrated jitter RMS at 155MHz Period jitter RMS Period jitter peak-to-peak Accumulated jitter RMS Accumulated jitter peak-to-peak Random Jitter
Integrated jitter RMS at 622MHz
Measured on Wavecrest SIA 3000
PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS At 155.52MHz, with capacitive decoupling
between VDD and GND. Over 10,000 cycles
At 155.52MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles.
“RJ” measured on Wavecrest SIA 3000 Integrated 12 kHz to 20 MHz
At 622.08MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles
At 622.08MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles.
“RJ” measured on Wavecrest SIA 3000 Integrated 12 kHz to 20 MHz
2.5 2.5 2.5 0.3 11 11 3 1.6
0.4 1.8
18.5 20 24 27 ps ps ps ps ps ps ps ps
45 49 24 27 6. Phase Noise Specifications
PARAMETERS FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS Phase Noise relative to carrier
155.52MHz -75 -95 -125 -140 -145 dBc/Hz
622.08MHz -75 -95 -110 -125 -120 Note: Phase Noise measured at VCON = 0V
7. CMOS Electrical Specifications
Output drive current
(High Drive) Output drive current (Standard Drive)
Output Clock Rise/Fall Time (Standard Drive)
Output Clock Rise/Fall Time (High Drive)
IOH IOL IOH IOL
PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS VOH= VDD-0.4V, VDD3.3V 30 VOL = 0.4V, VDD = 3.3V 30
VOH= VDD-0.4V, VDD3.3V 10 VOL = 0.4V, VDD = 3.3V 10 0.3V ~ 3.0V with 15 pF load 0.3V ~ 3.0V with 15 pF load
2.4 1.2
ns
mA mA
mA mA
* Note: High Drive CMOS is available on PLL520-06 through DRIVSEL selector input on pin 12.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 4
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8. LVDS Electrical Characteristics
PLL520-05/-06/-07/-08/-09
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Output Differential Voltage
VDD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage
Offset Magnitude Change Power-off Leakage Output Short Circuit Current
VOD 247 355 454 mV -50 50 mV ∆VOD
VOH 1.4 1.6 V RL = 100 Ω
(see figure) VOL 0.9 1.1 V VOS 1.125 1.2 1.375 V 0 3 25 mV ∆VOS
Vout = VDD or GND
uA IOXD ±1 ±10
VDD = 0V
IOSD -5.7 -8 mA 9. LVDS Switching Characteristics
PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time Differential Clock Fall Time
LVDS Levels Test Circuittr tf
RL = 100 Ω
CL = 10 pF (see figure)
0.2 0.7 1.0 ns 0.2 0.7 1.0 ns LVDS Switching Test CircuitOUT
OUT50ΩCL = 10pFVODVOSVDIFFRL = 100Ω50ΩCL = 10pFOUTOUTLVDS Transistion Time WaveformOUT0V (Differential)OUT80%VDIFF20%0V80%20%tRtF47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 5
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PLL520-05/-06/-07/-08/-09
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
10. PECL Electrical Characteristics
PARAMETERS SYMBOL CONDITIONS Output High Voltage Output Low Voltage
VOH VOL
RL = 50 to (VDD – 2V)
(see figure)
MIN. MAX. UNITS VDD – 1.025
VDD – 1.620
V V
11. PECL Switching Characteristics
PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Clock Rise Time
Clock Fall Time
tr tf
@20/80% - PECL @80/20% - PECL
0.6 0.5
1.5 1.5
ns ns
PECL Levels Test CircuitOUTVDDOUTPECL Output Skew50Ω2.0V50%50ΩOUTOUTtSKEWPECL Transistion Time WaveformDUTY CYCLE45 - 55%55 - 45%OUT80%50%20%OUTtRtF47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 6
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PLL520-05/-06/-07/-08/-09
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
PACKAGE INFORMATION
16 PIN TSSOP ( mm )SymbolMin.Max.A-1.20A10.050.15B0.190.30C0.090.20D4.905.10 E4.304.50 H6.40BSCL0.450.75e0.65BSCEHDAA1eBCL 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 7
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PLL520-05/-06/-07/-08/-09
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL520-0x O C PACKAGE TYPE O=TSSOP Q=QFN PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL Order Number Marking Package Option PLL520-05OC P520-05OC 16-Pin TSSOP (Tube) PLL520-05OC-R P520-05OC 16-Pin TSSOP (Tape and Reel) PLL520-05QC P520-05QC 16-Pin 3x3 QFN (Tube) PLL520-05QC-R P520-05QC 16-Pin 3x3 QFN (Tape and Reel) PLL520-06QC P520-06QC 16-Pin 3x3 QFN (Tube) PLL520-06QC-R P520-06QC 16-Pin 3x3 QFN (Tape and Reel) PLL520-07OC P520-07OC 16-Pin TSSOP (Tube) PLL520-07OC-R P520-07OC 16-Pin TSSOP (Tape and Reel) PLL520-08OC P520-08OC 16-Pin TSSOP (Tube) PLL520-08OC-R P520-08OC 16-Pin TSSOP (Tape and Reel) PLL520-08QC P520-08QC 16-Pin 3x3 QFN (Tube) PLL520-08QC-R P520-08QC 16-Pin 3x3 QFN (Tape and Reel) PLL520-09OC P520-09OC 16-Pin TSSOP (Tube) PLL520-09OC-R P520-09OC 16-Pin TSSOP (Tape and Reel) PLL520-09QC P520-09QC 16-Pin 3x3 QFN (Tube) PLL520-09QC-R P520-09QC 16-Pin 3x3 QFN (Tape and Reel) PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 8
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